1. Field of the Invention
This invention is directed to the manufacture of semiconductor components and, in particular, to the formation of field effect transistors having decreased resistance.
2. Description of Related Art
Typically, in forming a field effect transistor (FET), a silicon substrate is provided having diffusion areas and isolation trenches formed thereon. The substrate may be a silicon on insulator (SOI) substrate with shallow trench isolations. Diffusion areas such as N-wells and P-wells are formed by implantation and annealing methods well known in the art.
An oxide may be grown and polysilicon deposited on the surface of the substrate, patterned with a photoresist, and etched to form desired gate structures. Once the polysilicon gate structures are in place, spacers are formed adjacent to the gates to tailor the FET appropriately and prevent shorting of the gate to the diffusion areas. A conformal dielectric layer of silicon nitride or silicon oxide is deposited over the substrate and gate structures. The conformal dielectric layer is then isotropically etched to leave side wall spacers on either side of each gate structure.
To form the source and drain regions on the FET, dopants such as boron, and phosphorus are implanted into the wafer. A photoresist is applied to the substrate and patterned. The pattern leaves exposed areas on the substrate where a first dopant, for example a P+ dopant, is implanted to form a P+ source region and P+ drain region as well as dope the polysilicon gate structures. Thereafter, the photoresist is stripped and a reverse photoresist is applied which has a pattern corresponding to a N+ dopant. The second dopant is then imbedded into the wafer. Once the source and drain regions are formed, the wafer is annealed to activate the source and drain regions.
Typically, once the source and drain regions are formed, a metal is deposited on the surface of the wafer to form the metal silicide which reduces the resistance of the polysilicon lines. However, contaminants from the previous processing may cause discontinuities in the metal silicide formation by preventing the metal from fully reacting with the polysilicon. The discontinuities increase the resistance of the polysilicon lines and the source and drain regions.
Prior to silicide formation, the wafer is typically cleaned by a series of wet and dry cleans to remove contaminants. These cleans are intended to remove contaminants such as resist residuals, implant residuals, metals, and particles from the surface of the silicon wafer. However, these cleans while removing some or all of the native oxide do not remove more than a few mono-layers of silicon from the substrate and are insufficient to substantially remove all contaminants.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of removing contaminants from a surface and a top layer of a silicon wafer prior to silicide formation to reduce discontinuities in the metal silicide.
It is another object of the present invention to provide a method of forming a metal silicide having lower resistance on a silicon wafer.
A further object of the present invention is to provide a method of forming a field effect transistor having reduced resistance in the polysilicon lines and the source and drain regions.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.